Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL with numerous design examples to help the reader thoroughly understand this popular hardware description language. The Verilog HDL designs include the design module, the test bench module that tests the design for correct functionality, the outputs obtained from the test bench, and the waveforms obtained from the test bench. Each chapter contains numerous problems of varying complexity to be designed by the reader using Verilog HDL design techniques. All designs are carried through to completion-nothing is left unfinished or partially designed. The book is intended to be a tutorial, and as such, is comprehensive and self-contained. The use of mixed logic parallels the use of these symbols in the industry. Many analysis and synthesis examples use mixed-logic symbols incorporating both positive- and negative-input logic gates for NAND (not AND) and NOR (not OR) logic, while other examples utilize only positive-input logic gates. Each method that is presented is expounded in sufficient detail with accompanying examples. ![]() ![]() Each step of the analysis and synthesis procedures is clearly delineated. ![]() Emphasis is placed on structured and rigorous design principles that can be applied to practical applications. The book concentrates on sequential logic design with a focus on the design of various Verilog HDL projects. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995. Sequential Logic and Verilog HDL Fundamentals discusses the analysis and synthesis of synchronous and asynchronous sequential machines.
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